1) Field of the Invention
The present invention relates to, for a large-scale information processing apparatus including at least a plurality of storage units and a plurality of system controllers sharing communication control with respect to the plurality of storage units, a technique of fulfilling a memory access request with respect to the plurality of storage units.
2) Description of the Related Art
In general, a large-scale information processing apparatus equipped with a plurality of CPUs (Central Processing Units), I/O (Input/Output) units and other units is provided with a plurality of system controllers comprising, for example, LSI (Large Scale Integration) for controlling the communications between memory access requests, issued from these CPUs, I/O units and others, and storage units mounted in the CPUs.
FIG. 6 is a block diagram showing a configuration of a conventional large-scale information processing apparatus 100. As shown in FIG. 6, the conventional large-scale information processing apparatus 100 is equipped with system boards A and B, and the system board A has CPUs 10, 11 and I/O units 20, 21 while the system board B has CPUs 12, 13 and I/O units 22, 23.
Each of the CPUs 10 to 13 includes a plurality of cache memory hierarchized (in this case, two layers). That is, a primary cache memory 10a and a secondary cache memory 10b are included in the CPU 10, a primary cache memory 11a and a secondary cache memory 11b in the CPU 11, a primary cache memory 12a and a secondary cache memory 12b in the CPU 12, and a primary cache memory 13a and a secondary cache memory 13b in the CPU 13.
In addition, the system board A is equipped with main memories 30 and 31, and the system board B is equipped with main memories 32 and 33.
Still additionally, the system board A has a system controller 40-1 designed to carry out the communication control with respect to the storage units (in this case, the primary cache memories 10a, 11a, the secondary cache memories 10b, 11b, and the main memories 30, 31) mounted on the system board A.
The system board B has a system controller 40-2 designed to carry out the communication control with respect to the storage units (in this case, the primary cache memories 12a, 13a, the secondary cache memories 12b, 13b, and the main memories 32, 33) mounted on the system board B.
Thus, the system controllers 40-1 and 40-2 share or bear the communication control relative to the plurality of storage units provided in the information processing unit 100 and similar in configuration to each other except the storage units which are an object of communication control. These system controllers 40-1 and 40-2 are connected to be communicable with each other.
The system controller 40-1 is made up of a memory access request receiving unit 41-1, a retrieval unit 42-1, a broadcast transmitting/receiving unit 43-1, a global snoop control unit 44-1 and a memory access control unit 45-1.
The memory access request receiving unit 41-1 is made to receive a memory access request issued from one of the CPUs 10, 11 and the I/O units 20, 21.
The retrieval unit 42-1 is for, in response to an issue of a memory access request, retrieving the data to be accessed (which will hereinafter be referred to simply as target data) on this memory access request from the storage units the system controller 40-l takes charge of (assigned thereto), in this case, from the primary cache memories 10a, 11a, the secondary cache memories 10b, 11b and the main memories 30, 31.
The broadcast transmitting/receiving unit 43-1 is for, when an issue of a memory access request takes place, transmitting/receiving a retrieval instruction (retrieval request) for the retrieval of the target data on (related to) the memory access request to/from the other system controller 40-2, thus retrieving the target data on the memory access request from all the storage units provided in the information processing apparatus 100. That is, the broadcast transmitting/receiving unit 43-1 broadcasts a retrieval instruction (indication) to the other system controller 40-2 when the memory access request receiving unit 41-1 receives a memory access request, and receives a retrieval instruction when the retrieval instruction is broadcasted from the other system controller 40-2.
In accordance with the retrieval instruction transmitted/received by the broadcast transmitting/receiving unit 43-1, the global snoop control unit 44-1 makes the retrieval unit 42-1 retrieve the target data on the memory access request from the assigned storage units (in this case, the primary cache memories 10a, 11a, the secondary cache memories 10b, 11b, and the main memories 30, 31) and, through the communications of retrieval results with respect to the other system controller 40-2, determines an operation for the memory access request on the basis of the retrieval result in the other system controller 40-2 and its own retrieval result.
The memory access control unit 45-1 is for fulfilling the memory access request on the basis of the operation to the memory access request determined in the global snoop control unit 44-1.
The memory access request receiving unit 41-2, the retrieval unit 42-2, the broadcast transmitting/receiving unit 43-2, the global snoop control unit 44-2 and the memory access control unit 45-2 provided in the system controller 40-2 are similar to the memory access request receiving unit 41-1, the retrieval unit 42-1, the broadcast transmitting/receiving unit 43-1, the global snoop control unit 44-1 and the memory access control unit 45-1 in the system controller 40-1, respectively, except that the objects of communication control are the primary cache memories 12a, 13a, the secondary cache memories 12b, 13b and the main memories 32, 33.
FIG. 7 is a time chart for explaining an operation of the conventional large-scale information processing apparatus 100. As shown in FIG. 7, when a memory access request (in this case, a data fetch request; hereinafter referred to as a fetch request) is issued from the CPU 10 (see t1) and the memory access request receiving unit 41-1 of the system controller 40-1 receives the fetch request issued from the CPU 10 (see t2), the broadcast transmitting/receiving unit 43-1 broadcasts a retrieval instruction for the target data on the fetch request to the other system controller 40-2 for retrieving the target data on the fetch request from all the storage units (see t3).
Following this, when the broadcast of the retrieval instruction by the broadcast transmitting/receiving unit 43-1 reaches completion, the global snoop control units 44-1 and 44-2 make the retrieval units 42-1 and 42-2 carry out the retrieval (snoop) on the basis of the transmitted/received retrieval instruction in a synchronized condition (see t4).
Subsequently, when the retrievals by the retrieval units 42-1 and 42-2 reach completion, the global snoop control units 44-1 and 44-2 communicate the retrieval results to each other in a synchronized condition (see t5) and makes a decision on a final operation for the fetch request in accordance with the retrieval results and determine it (see t6).
At this time, in a case in which retrieval unit 42-1 retrieves the target data on the fetch request from the primary cache memory 11a or the secondary cache memory 11b (in this case, the primary cache memory 11a) of the CPU 11 and the global snoop control units 44-1 and 44-2 determine the readout of the target data from the primary cache memory 11a with respect to the fetch request, the memory access control unit 45-1 issues a readout (read) request for the target data on the fetch request to the primary cache memory 11a of the CPU 11 (see t7) to read out the target data on the fetch request from the primary cache memory 11a into the system controller 40-1 (see t8 and t9), and the memory access control unit 45-1 then transmits the target data, read out from the primary cache memory 11a, as a fetch data response to the CPU 10 (see t10 and t11). Thus, the implementation of the fetch request reaches completion.
As described above, in the conventional large-scale information processing apparatus 100, with respect to a memory access request issued, communications are made among the plurality of system controllers 40-1 and 40-2 to make a decision and determination on the processing for this memory access request. At this time, the broadcast processing (see t3 in FIG. 7) and the retrieval result communication processing (see t5 in FIG. 7) to be conducted between the system controllers 40-1 and 40-2 take time and, hence, the conventional large-scale information processing apparatus 100 requires a long time from when a memory access request occurs until this memory access request is fulfilled.
That is, in the conventional large-scale information processing apparatus 100, of the time to be taken for the entire processing to a memory access request, the time to be needed for the broadcast processing and the retrieval result communication processing for the retrieval of the target data on the memory access request absorbs a large percentage.
For this reason, for shortening the time to be needed for the processing on a memory access request, in the information processing apparatus 100, in a case in which the operation on the memory access request can be determined on the basis of only the retrieval result in the retrieval unit 42-1, the global snoop control unit 44-1 is made so as to determine and carry out the operation on the memory access request without making a communication between the plurality of global snoop control units 44-1 and 44-2.
FIG. 8 is a time chart in a case in which, in the conventional large-scale information processing apparatus 100, of the processing for the memory access request, the communication processing on the retrieval result is not conducted between the plurality of system controller 40-1 and 40-2.
That is, as shown in FIG. 8, when the memory access request receiving unit 41-1 of the system controller 40-1 receives a memory access request (see t1 and t2), after the broadcast transmitting/receiving unit 43-1 transmits/receives a retrieval instruction (see t3), if, as the result of the retrieval (snoop) of the target data on the memory access request in the retrieval unit 42-1 (see t4), the retrieval unit 42-1 retrieves the target data from the assigned storage units and the type of the memory access request, the registration state of the target data and others satisfy a predetermined condition, the global snoop control unit 44-1 determines and carries out an operation on the memory access request without making a communication on the retrieval result with respect to the other global snoop control unit 44-1 (see t7 to t11).
A description will be given hereinbelow of a case (the aforesaid predetermined condition) in which the global snoop control unit 44-1 can determine an operation for a memory access request on the basis of only a retrieval result in the retrieval unit 42-1. In the conventional information processing apparatus 100, there are the following cases (1) to (3) as the cases in which the global snoop control unit 44-1 can determine an operation for a memory access request on the basis of only the retrieval result in the retrieval unit 42-1.
(1) A case in which, like an example shown in FIG. 8, an issued memory access request is a fetch request and this fetch request is a sharing type fetch request for only fetching target data from one of the plurality of storage units and the retrieval unit 42-1 retrieves the target data from the assigned storage units.
(2) A case in which a fetch request serving as a memory access request is an exclusive fetch instruction whereby the target data is retained in only one storage unit of a plurality of storage units (in this case, the primary cache memories 10a to 13a, the secondary cache memories 10b to 13b and the main memories 30 to 33) and the target data is retrieved from the storage unit, the retrieval unit 42-1 takes charge of, and the retrieved target data is exclusive data which is retained in only one storage unit but not retained in the other storage units.
(3) A case in which an issued memory access request is a store instruction and the target data is retrieved from the storage unit, the retrieval unit 42-1 takes charge of, and the retrieved target data is exclusive data.
Thus, in the conventional large-scale information processing apparatus 100, the communication processing on the retrieval result between the global snoop control units 44-1 and 44-2 is omissible only in the above-mentioned cases (1) to (3).
Incidentally, as the technique for retaining data in an exclusive manner, there has been known a technique (see Japanese Patent Laid-Open Nos. HEI 6-250926 and HEI 11-259361) of making registration so that, in a CPU having a plurality of cache memories arranged hierarchically, data is retained in only one cache memory.
In addition, there has been proposed a technique of, in a case in which a plurality of cache memories arranged hierarchically share and retain data, maintaining the consistency (agreement) of the data shared in the respectively memories (see Japanese Patent Laid-Open Nos. HEI 5-2534 and HEI 6-187239).
Meanwhile, in the above-described conventional large-scale information processing apparatus 100, of the communication processing to be conducted between the system controllers 40-1 and 40-2, the time (see t3 in FIG. 7) needed for the transmission/reception of a retrieval instruction between the broadcast transmitting/receiving units 43-1 and 43-2 is approximately equal to the time (see t5 in FIG. 7) needed for the communication processing on a retrieval result between the global snoop control units 44-1 and 44-2.
However, in the conventional large-scale information processing apparatus 100, although, in the case of the above-mentioned (1) to (3), the communication processing on the retrieval result between the global snoop control units 44-1 and 44-2 is omissible, the transmission/reception processing on a retrieval instruction to be conducted between the broadcast transmitting/receiving units 43-1 and 43-2 is not omissible in any case and, hence, much time is still required from when a memory access request occurs until the fulfillment of this memory access request.
Moreover, although the description has been given above of the example shown in FIG. 6 where the information processing apparatus 100 is equipped with two system controllers (system controllers 40-1 and 40-2), if the information processing apparatus 100 has a larger-scale arrangement including more-than-two system controllers, there is a need to mount the system controllers in a state of crossing a plurality of bodies of equipment, or to newly use an LSI for the communication control between the system controllers. This further increase the time to be taken for the communication processing between the system controllers and requires longer time from when a memory access request occurs until the fulfillment of that memory access request.